1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and more particularly, to a technique for solving various problems caused by difference in depths of contact holes in forming a semiconductor device having a plurality of contact holes of different depths.
2. Description of the Background Art
A conventional semiconductor device having a plurality of contact holes of different depths and a method of manufacturing thereof will be described hereinafter taking a DRAM (Dynamic Random Access Memory) as an example.
FIG. 19 is a sectional view of a memory cell portion of a DRAM having a memory cell called a stacked capacitor structure. Referring to FIG. 19, a memory cell of a conventional stacked capacitor structure has a MOS (metal oxide semiconductor) type field effect transistor formed on an active region isolated by a field insulating film 2 on the surface of a semiconductor substrate 1, and a capacitor having a stacked structure formed in the proximity thereof. The MOS type field effect transistor has impurity diffusion regions 3 and 4 which become the source/drain region formed on the surface of the semiconductor substrate 1, and a gate electrode 6a which becomes a word line formed on the surface of the semiconductor substrate in the region sandwiched between the impurity diffusion regions 3 and 4 with a gate insulating film 5 thereunder. A plurality of word lines are arranged in parallel. A gate electrode 6b is located on the field insulating film 2 parallel to the gate electrode 6a. On insulating film 7a and 7b covering the gate electrodes 6a and 6b, respectively, a lower electrode 8, an upper electrode 10, and a dielectric film 9 sandwiched therebetween of a capacitor which becomes the storage node are formed.
The lower electrode 8 of the capacitor is electrically connected to the impurity diffusion region 4 in a contact hole 4a. On the upper electrode 10 of the capacitor, a conductive layer 12 which becomes a bit line is formed with an interlayer insulating film 11 therebetween. The conductive layer 12 is electrically connected to the impurity diffusion region 3 in a contact hole 13 provided in the interlayer insulating film 11.
A relatively planar interlayer insulating film 14 is formed on the conductive layer 12. A conductive layer 15 having a two layered structure of a barrier metal layer 15a such as of TiN and an aluminum alloy layer 15b such as of Al-Si-Cu is formed on the surface of the interlayer insulating film 14. The conductive layer 15 is conductive with the gate electrodes 6a and 6b via a contact hole in a position not seen in the sectional view of FIG. 19. The conductive layer 15 is an interconnection for the purpose of improving conductivity of a word line, and an interconnection that is electrically connected to the surface of the semiconductor substrate 1 or to the surface of the upper electrode 10 of the capacitor in a peripheral circuit portion of the memory cell. A passivation film 16 is formed covering the conductive layer 15 on the interlayer insulating film 14.
The DRAM structured as described above has the conductive interconnection 15 and the semiconductor substrate 1, or the conductive interconnection 15 and the upper electrode 10 of the capacitor electrically connected via a contact hole formed in the interlayer insulating film in the peripheral circuit portion thereof.
The contact hole 20 for electrically connecting the conductive interconnection 15 and the surface of semiconductor substrate 1 is relatively high (i.e. has a depth of d.sub.1) if the interlayer insulating films 17, 18 and 19 are subjected to thermal process for planarization, as shown in FIG. 20, and is formed by anisotropic etching using a resist mask 21 as the mask. If planarization process of the interlayer insulating films 17, 18 and 19 is not carried out, the contact hole 20 is relatively shallow (i.e. has a depth d.sub.2 : d.sub.2 &lt;d.sub.1), as shown in FIG. 21. The contact hole 22 for electrically connecting the conductive interconnection 15 to the upper electrode (cell plate) 10 of the capacitor does not penetrate the interlayer insulating film 17 as shown in FIG. 22, and is formed relatively shallow (d.sub.3 &lt;d.sub.1, d.sub.2) with a resist mask 23 as the mask since the interlayer insulating films 18 and 19 at this position are relatively thin in comparison with the position shown in FIG. 20.
The difference in depth of contact holes 20 and 22 in relation to the thickness of the interlayer insulating films 17, 18 and 19 are shown in specific numeric figures in the following Table 1.
TABLE 1 ______________________________________ Comparison of Contact Hole Depth (unit: angstrom) Penetrated Interlayer Insulating Film Contact hole 20 Contact hole 22 ______________________________________ Interlayer Insulating Approximately 1300 Not Penetrated Film 17 Interlayer Insulating 5000-8500 Approximately 5000 Film 18 Interlayer Insulating 4000-6000 Approximately 4000 Film 19 Contact hole Depth 10300-15800 Approximately 9000 ______________________________________
The reason why the interlayer insulating films 18 and 19 through which the contact hole 20 penetrates have a thickness of a predetermined range is as set forth in the following.
In the case where the contact hole 20 is formed at a valley sandwiched by two regions where an element such as a transistor is formed, as shown in FIGS. 20 and 21, the interlayer insulating films 18 and 19 are planarized by the reflow of a thermal treatment, or by etching back the whole surface by dry etching. It can be appreciated from the comparison of FIGS. 20 and 21 that the thickness at the position for forming the contact hole 20 in the interlayer insulating film 18 and 19 is increased in FIG. 20 where a planarization process is applied in comparison with FIG. 21 where a planarization process is not applied. If a planarization process is not carried out as shown in FIG. 21, the interlayer insulating films 18 and 19 at the position for forming the contact hole 20 is relatively thin, whereby the depth of the contact hole 20 is smaller than the depth of d in the case of FIG. 20. Although this is advantageous from the standpoint of reducing the time required for etching the contact hole 20, a stepped portion will be generated between the region for forming the contact hole 20 and the adjacent region where an element is formed due to difference in the thickness of the interlayer insulating films 18 and 19. This stepped portion will cause resolution deficiency in the resist pattern because a stepped portion exceeding the depth of focus of the exposure device is generated at the time of photolithography for forming the contact hole 20, or at the time of a later photolithography for a conductive interconnection at a later process. Also, if the conductive interconnection is formed of aluminum interconnection and the photolithography process is carried out using a positive resist, an undesirable phenomenon called halation occurs in which the resist pattern for conductive interconnection is exposed and eliminated due to light reflectance from the underlying stepped portion during exposure, in addition to the above described resolution deficiency.
A planarization process for each interlayer insulating film is indispensable to suppress such undesirable phenomenon, and the thickness of the oxide film of the contact hole formation portion depends upon the planarization process.
Referring to FIG. 22 which is a sectional view showing a formation step of the contact hole 22 on the upper electrode (cell plate) 10 of the capacitor, the film thickness of the region for forming the contact hole is not increased even after the above-described planarization process because there is no word line below the upper electrode 10. Also, because the contact hole 22 does not penetrate the interlayer insulating film 17, the depth d.sub.3 of the contact hole 22 is smaller by approximately 6000-7000.ANG. in comparison with the case shown in FIG. 20 where the contact hole 20 has a depth of d.sub.1.
Because a conventional semiconductor device is formed as above with a contact hole 20 of a relatively great depth and a contact hole 23 of a relatively small depth, a process of etching both holes simultaneously will result in the doped polysilicon of the underlying upper electrode 10 of the capacitor being etched to form a hole as shown in FIG. 23 because the contact hole 23 will be excessively overetched if the etching time is set to form thoroughly the contact hole 20. Therefore, when a conductive interconnection having a double structure of a barrier metal layer 31 such as of TiN and an aluminum alloy layer 32 is formed in the contact hole 22, as shown in FIG. 24, the junction between the barrier metal 31 and the upper electrode 10 will be established only at a small region along the inner perimeter of the contact hole 20 to become the cause of conduction deficiency.
Even if the doped polysilicon layer of the upper electrode 10 is not thoroughly penetrated, and the film thickness of the upper electrode 10 is reduced to less than approximately 700.ANG. as shown in FIG. 25, alloy is made of the Ti of the barrier metal layer and the polysilicon, i.e. formation of a TiSi.sub.2 layer 33 progresses due to silicidation as shown in FIGS. 26 and 27 because of being subjected to a high temperature of 800.degree. C. in lamp annealing under an N.sub.2 ambient for the formation of a barrier metal 31. As a result, the doped polysilicon at the bottom of the contact hole 20 and also in the proximity of the side portion of the bottom of the contact hole is absorbed by the Ti to generate a void 34 which is shown in enlargement in FIG. 27. If the void 34 is significant, the upper electrode 10 is disconnected in the worst case. The limitation of the film thickness of a doped polysilicon layer in which a void 34 is generated is generally approximately 700.ANG. although depending on the film nature of the Ti and the lamp anneal temperature. It is therefore necessary to set the film thickness of the doped polysilicon layer to be approximately 1000.ANG. after the formation of a contact hole by dry etching and taking into consideration a manufacturing error margin. It is desired that the generation of the void 34 is prevented without increasing the film thickness in order to reduce the film thickness of the device.
The limitation of adjusting the etching time period will be described hereinafter. In general, the etching time T of dry etching for forming a contact hole is set by including to the etching time T.sub.1 for forming just the deepest contact hole, an overetching time T.sub.2 taking into consideration error in the designed film thickness of each interlayer insulating film which is the film to be etched and the variation error of the etching rate of the dry etching device, i.e. T=T.sub.1 +T.sub.2. The variation error of the etching rate of the dry etching device is caused by difference in the etching rate between semiconductor wafers, difference in the etching rate between wafers, and difference in the etching rate between batches in the case of a batch system dry etching. The film thickness distribution among semiconductor wafers and the distribution of the etching rate are shown in FIG. 28A and 28B. In the case where the thickness of the film to be etched moves towards the thinner direction (in the direction of arrow A in FIG. 28) and the etching rate moves towards the faster rate (in the direction of arrow D in FIG. 28B), there is a high probability of the doped polysilicon of the upper electrode 10 (cell plate) of the capacitor being overetched as shown in FIGS. 23 and 25. Conversely, in the case where the thickness of the film to be etched moves towards the thicker direction (the direction of arrow B in FIG. 28A) and the etching rate move towards a slower rate (the direction of arrow C of FIG. 28B), the deepest contact hole is not thoroughly formed. In the case of the contact hole 20 shown in FIG. 20, there is a high probability of the conductance between the conductive interconnection formed on the interlayer insulating film 19 and the surface of the semiconductor substrate 1 being not established. If the overetching time T.sub.2 is increased, the probability of the generation of the latter will be reduced, but the probability of generation of the former will increase. Conversely, if T.sub.2 is reduced, the probability of the former will be decreased but the probability of the latter will increase. By analyzing the test result of good product selection, the probability occurrence thereof was 5% at 3.sigma. respectively.
Although the probability of the problem will be reduced if the thickness of the doped polysilicon of the upper electrode (cell plate) 10 of the capacitor is increased, such an increase in thickness will result in a greater stepped portion with a greater possibility of the trouble at a later processing step. It is not desirable to employ the means of increasing the film thickness since reduction of the film thickness of each layer is a mandatory condition in the development of a semiconductor device of higher integration density.
The above-described problem becomes further significant in the case of coexistence of a contact hole 24 formed on the surface of the semiconductor substrate 1 and a contact hole 25 formed on the surface of a bit line 12 because the difference in the depth thereof is greater.
The following Table 2 shows the film thickness of the interlayer insulating films through which the contact hole 25 is penetrated and the depth of the contact holes 24 and 25 assuming that the film thicknesses of interlayer insulating films 17, 18 and 19 through which the contact hole 24 in FIG. 29 penetrates are identical to those of the contact hole 20 shown in FIG. 23.
TABLE 2 ______________________________________ Comparison of Contact Hole Depth (unit: angstrom) Penetrated Interlayer Insulating Film Contact hole 24 Contact hole 25 ______________________________________ Interlayer Insulating Approximately 1300 Not Penetrated Film 17 Interlayer Insulating 5000-8500 Not Penetrated Film 18 Interlayer Insulating 4000-6000 Approximately 4000 Film 19 Contact hole Depth 10300-15800 Approximately 4000 ______________________________________